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temperature sensor hub and fan controller data sheet adt7470 r ev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherw ise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures monitors up to 10 remote temperature sensors monitors and c ontrols speed of up to 4 fans independently pwm outputs drive each fan under software control full_speed input allows fans to be blasted to maximum speed by external hardware smbalert interrupt sign als failures t o system controller three - state addr pin allows up to 3 devices on a single bus temperature decoder interpret s tmp05 temperature sensors and communicate s values over i 2 c bus limit compa rison of all monitored values supports f ast i 2 c standard (400 khz max ) meets smbus 2.0 electrical specifications (full y smbus 1.1 - c ompliant) applications s ervers networking and telecommunications equipment desktops general description th e adt7470 1 contr oller is a multi channel temperature sensor and pwm fan controller and fan speed monitor for systems requiring active cooling. it is designed to interface directly to an i 2 c? bus. the adt7470 can monitor up to 10 daisy - chained tmp05 temperature sensors. i t can also monitor and control the speed of four fans, in automatic or in manual control loops. a full_speed input is pr ovided to allow the fans to be blasted to maximum speed, via external hardware control, under extreme thermal co nditions or on system startup. an smbalert interrupt communicates error conditions such as fan under speed and over temperature measurements to the system service processor. individual error conditions can then be read from status registers over the i 2 c bus . functional block dia gram full_speed pwm1 pwm2 pwm3 pwm4 tach1 tach2 tach3 tach4 tmp_start tmp_in addr sda scl smbalert address pointer register pwm config registers interrupt masking interrupt status registers limit comparators value and limit registers serial bus interface smbus address selection automatic fan speed control pwm registers and controllers fan speed counters temperature decoder 04684-0-001 adt7470 figure 1. 1 protected by patent numbers us6,169,442, us6,097,239, us5,982,221, us5,867,012. other patents pending.
adt7470 data sheet rev. e | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 serial bus timing specifications ................................................ 4 absolute maximum ratings ............................................................ 5 thermal characteristics .............................................................. 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 functional description .................................................................... 7 general description ..................................................................... 7 configuration register 1 (address 0x40) .................................. 7 configuration register 2 (address 0x74) .................................. 7 id registers ................................................................................... 7 general - purpose i/o pins (open drain) ...................................... 8 smbus/i 2 c serial interface .............................................................. 9 address selection ......................................................................... 9 serial bus protocol ....................................................................... 9 write operations ........................................................................ 11 read operations ......................................................................... 12 smbus timeout .......................................................................... 12 temperature measurement using tmp05/tmp06 ................... 13 measuring temperature ............................................................ 13 temperature readback by the host ........................................ 14 temperature data format ......................................................... 14 temperature measurement limits ........................................... 15 thermal zones for automatic fan control ............................ 15 limit and status registers ............................................................. 1 6 limit values ................................................................................ 16 temperature limits .................................................................... 16 fan speed limits ........................................................................ 16 out - of - limit comparisons ....................................................... 16 status registers ........................................................................... 17 smbalert interrupt ................................................................ 18 fan drive using pwm control .................................................... 20 high frequency fan drive ........................................................ 20 low frequency fan drive ......................................................... 20 setting the fan d rive frequency .............................................. 21 inverted pwm output .............................................................. 21 fan full speed function ............................................................ 21 fan speed measurement ................................................................ 22 tach inputs .................................................................................. 22 fan speed measurement ........................................................... 23 manual fan speed control ........................................................... 25 setting the pwm duty cycle ................................................... 25 automatic fan speed control ...................................................... 26 register map ................................................................................... 27 detailed register descriptions ..................................................... 29 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision history 4/13 rev. d to rev. e changed input low voltage, v il from 0.4 v to 1.0 v and added test conditions/comments; table 1 .............................................. 3 3 /13 rev. c to rev. d change s to calculating fan speed and tachometer limits section .............................................................................................. 24 changes to bit 3, table 43 .............................................................. 35 updated outline dimensions ....................................................... 3 9 7/09 rev. b to rev. c changes to functional description section ................................. 7 added temperature data form at section .................................. 14 additions to fan drive using pwm control section ............... 20 additions to manual fan speed control section ...................... 25 additions to automatic fan speed control section ................. 26 7/05 rev. a to rev. b references to pwm_in changed to tmp_in ............... universal change s to t min registers section .................................................. 7 added address selection s ection .................................................... 7 added thermal zones section ..................................................... 12 added temperature reading section .......................................... 13 added note to table 39 ................................................................. 32 2/05 rev. 0 to rev. a added general - purpose i /o pins (open drain) section ......... 11 11/04 revision 0: initial version
data sheet adt7470 rev. e | page 3 of 40 specifications t a = ? 40 o c to +125 o c , v cc = 3.0 v to 5.5 v, unless otherwise noted . table 1 . parameter 1 , 2 , 3 , 4 , 5 min typ max unit test conditions/comments power supply 1 supply voltage 3.0 3.3 5.5 v supply current, i cc 0.5 0.8 m a standby current, i cc 4 a fan rpm - to - digital converter accuracy 12 % full - scale count 65,535 nominal input rpm 109 rpm f an c ount = 0xbfff 329 rpm fan c ount = 0x3fff 5 , 000 rpm fan c ount = 0x0438 10, 000 rpm fan c ount = 0 x021c open - drain digital outputs, pwm1 to pwm4, smbalert output low voltage, v ol 0.4 v i out = C 8.0 ma, v cc = + 3.3 v high level output current, i oh 0.1 1 a v out = v cc open - drain serial data bus output (sda) output l ow voltage, v ol 0.4 v i out = C 4.0 ma, v cc = + 3.3 v high level output current, i oh 0.1 1 a v out = v cc smbus digital inputs (scl, sda) input high voltage, v ih 2. 4 v input low voltage, v il 1. 0 v v cc = 3.3 v hysteresis 500 mv digital inp ut logic levels (tach inputs, full_speed , gpio ) input high voltage, v ih 2. 4 v input low voltage, v il 0.8 v hysteresis 50 mv p -p digital input logic levels (t mp_in ) input high voltage, v ih v dd C 0.3 v input low voltage, v il 0. 4 v digital input current input high current, i ih C 5 a v in = v cc input low current, i il 5 a v in = 0 input capacitance, c in 5 pf 1 v dd should never be floated in the presence of scl/sda activity. charge injection ca n be sufficient to induce approximately 0.6 v on v dd. 2 all voltages are measured with respect to gnd, unless otherwise specified. 3 typical values are at %a = 25 c and represent the most likely parametric norm. 4 logic inputs accept i nput high voltages up to 5 v even when the device is operating at supply voltages below 5 v. 5 timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.0 v for a rising edge.
adt7470 data sheet rev. e | page 4 of 40 serial bus timing specifications table 2. parameter 1, 2, 3, 4, 5 min typ max unit test conditions/comments serial bus timing clock frequency, f sclk 400 khz see figure 2 glitch immunity, t sw 50 ns see figure 2 bus free time, t buf 1.3 s see figure 2 start setup time, t su;sta 600 ns see figure 2 start hold time, t hd;sta 600 ns see figure 2 scl low time, t low 1.3 s see figure 2 scl high time, t high 0.6 s see figure 2 scl, sda rise time, t r 300 ns see figure 2 scl, sda fall time, t f 300 ns see figure 2 data setup time, t su;dat 100 ns see figure 2 detect clock low timeout, t timeout 25 28 31 ms can be optionally disabled, via configuration register 1 (see table 6) 1 vdd should never be floa ted in the presence of scl/sda ac tivity. charge injection can be su fficient to induce approximately 0. 6 v on vdd. 2 all voltages are measured with respect to gnd, unless otherwise specified. 3 typical values are at %a = 25c and represent the most likely parametric norm. 4 logic inputs accept input high voltages up to 5 v even when the device is operating at supply voltages below 5 v. 5 timing specifications are tested at logic levels of vil = 0.8 v for a falling edge and vi h = 2.0 v for a rising edge. 04684-0-002 scl sda ps t buf t hd;sta t hd;dat t high t su;dat t hd;sta t su;sta t su;sto t low t r t f sp figure 2. serial bus timing diagram
data sheet adt7470 rev. e | page 5 of 40 absolute maximum rat ings table 3 . parameter rating positive supply voltage (v cc ) 6.5 v voltage on any t ach or pwm p in C 0.3 v to + 6.5 v voltage on any input or output pin C 0.3 v to v cc + 0.3 v maximum junc tion temperature (t j max) 150c storage temperature range C 65c to +150c lead temperature, soldering vapor phase , 60 sec 215c infrar ed , 15 sec 200c esd rating (hbm) 30 00 v thermal characterist ics 16- lead qsop package: ja = 105c/w jc = 39c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adt7470 data sheet rev. e | page 6 of 40 pin configuration an d function descriptions 04684-0-003 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 gnd v cc tach3 tach2 tach1 pwm2 scl pwm1 smbalert full_speed/tmp_start pwm4 pwm3 tach4 addr tmp_in sda adt7470 top view (not to scale) figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 scl digital input (open drain). smbus serial clock input. requires smbus pull -up , typically 2k2 ?. 2 gnd groun d pin . 3 v cc power supply pin. 4 tach3 digital input (open drain). fan tachometer input to measure the speed of fan 3. 5 pwm2 digital i/o (open drain). requires 10 k? typical pull - up. pulse - width modulated output to control the speed o f fan 2. can be configured as gpio by setting b it 0x7f [ 2 ] = 1 . 6 tach1 digital input (open drain). fan tachometer input to measure the speed of fan 1. 7 tach2 digital input (open drain). fan tachometer input to measure the speed of fan 2. 8 pwm3 digital i/o (open drain). pulse - width modulated output to control the speed of fan 3 . requires 10 k? typical pull - up. can be configured as gpio by setting bit 0x7f[ 1 ] = 1. 9 tach4 digital input (open drain). fan tachometer input to measure the speed of fan 4. 10 pwm4 digital i/o (open drain). pulse - width modulated output to control the sp eed of fan 4. requires 10 k? typical pull - up. can be configured as gpio by setting bit 0x7f[ 0 ] = 1. 11 addr three - state input . u sed to set the smbus device address. 12 tmp _in digital input (open drain ). pwm input to pwm processing engine that interprets daisy - chained output from multiple tmp05 temperature sensors. readings from individual tmp05 temperature sensors are available by reading the temperature reading registers over the smbus. 13 full_speed digital input active low (o pen drain) . this input blast s the fans to maximum speed when the pin is pulled low externally. do not leave pin 13 open when not i use, tie to v cc. 13 tmp_start digital output (open drain). this pin can be used as an o utput to start daisy - chained tempera ture measurements from tmp05 or tmp06 temperature sensors. requires 10 k? typical pull - up. 14 smbalert digital output active low (open drain). this pin can be reconfigured as an smbalert interrupt output to s ignal out - of - limit conditions such as fan failures. 15 pwm1 digital i/o (open drain). pulse - width modulated output to control the speed of fan 1. requires 10 k? typical pull - up. ca n be configured as gpio by setting b it 0x7f [ 3 ] = 1 . 16 sda digital i/o (o pen drain). smbus bidirectional serial data. requires smbus pull -up , typically 2k2 ?.
data sheet adt7470 rev. e | page 7 of 40 functional descripti on general description the adt7470 is a multi channel , pulse - width modulation ( pwm ) fan controller and moni tor for any system requiring monitoring an d cooling. the device communicates with the system via a serial system management bu s. the device has a single ad dre ss line for address selection (p in 11), a serial data line for reading and writing addresses and data ( p in 16), and an input line for the serial clock ( p in 1). all control and programming functions of the adt7470 are performed over the serial bu s, which supports both smbus and f ast i 2 c speci - fications. in addition, an smbalert interrupt output is provided to indicate out - of - limit conditions. when the adt7470 monitoring sequence is s tarted, it cycles through each fan tach input to measure fan speed. measured values from these inputs are stored in value registers. these can be read out over the serial bus, or they can b e automatically compared with programmed limits stored in the limi t registers. the results of out - of - limit comparisons are stored in the status registers, which can be read over the serial bus to flag out - of - limit conditions. if fan speeds drop below prese t levels or a fan stalls, an interrupt is generated . likewise , the adt7470 can flag fan over speed conditions by using limits set in the fan tach m ax imum registers. adt7470 monitoring cycle the monitoring cycle begins when a 1 is written to the start bit (bit 0) of configuration register 1 (register 0x40). each fan tach input is monitored in turn, and, as each measurement is completed, the result is automatically stored in the appropri - ate value register. multiple temper ature channels can also be moni tored by clocking in temperatures using the tmp_in pin. the temperature measurement function is addressed in hardware and requires no software intervention. the monitoring cycle continues unless disabled by writing a 0 to bit 7 of configuration register 1. the rate of tempe rature measurement updates depend s on the nominal conversion rate of the tmp05/ tmp 06 te mperature sensor (approx imately 120 ms) an d on the number of tmp05s daisy - chained together. the total monitoring cycl e time is the temperature conve rsion time multiplied by the number of temperature channels being monitored . fan tach measurements are taken in parallel and are not syn - chronized with the temperature measurements in any way configuration regist er 1 (address 0x40) this register contains t he s trt bit, b it 0, which b egins the monitoring cycle on t he adt7470. the smbus timeout can be disabled , fast tach enabled, and the registers locked, by writing to this register. control of high or low frequency fan dri ve , and the config - uration for p in 1 3, can be accessed via this register. see table 31 for more details. configuration regist er 2 (address 0x74) writing a 1 to b it 0 in this register puts the adt7470 in shutdown mode, which puts the part into a low current consump tion mode. the pwm frequency for each fan is controlled via this register. fan speed measurement can be disabled for each fan by writing to this register. see table 44 for more details. id registers the adt7470 has three read - onl y registers for identifying the part and silicon revision. the device id register is located at address 0x3d, and is set to 0x70. the company id register, located at address 0x3e, is set to 0x41. the revision number register is at address 0x3f, and con tains the revision number of the adt7470 silicon.
adt7470 data sheet rev. e | page 8 of 40 general - purpose i/o pins (op en drain) the ad t7470 has four pins that can be configured as either general - purpose logic pins or as pwm out puts . each gpio pin has a corresponding enable, direction, polarit y and status bit. pin function register address and bit gpio1 enable 0x7f [ 3] direction 0x80 [7] polarity 0x80 [6] status 0x81 [4] gpio2 enable 0x7f [2] direction 0x80 [5] polarity 0x80 [4] status 0x81 [5] gpio3 enable 0x7f [1] direction 0x80 [3] polarity 0x80 [2] status 0x81 [6] gpio4 enable 0x7f [0] direction 0x80 [1] polarity 0x80 [0] status 0x81 [7] to enable the pwm output on the adt747 0 as gpios, the enable bits in r egister 0x7f must be set to 1. setting a direction bit to 1 in the gpio configuration register makes the corresponding gpio pin an output. clearing the direction bit to 0 makes it an input. setting a polarity bit to 1 makes the corresponding gpio pin active high. clearing the polarity bit to 0 makes it active low. when a gpio p i n is configured as an input, the corresponding bit in the gp io status register is read - only and is set when the input is asserted. when a gpio pin is configured as an output, the corresponding bit in one of the gpio status registers be comes read/write. setting this bi t asserts the gpio output . note that whether a gpio pin is configure d as an input or as an output, asserted can be high or low , depending on the setting of the polarity bit .
data sheet adt7470 rev. e | page 9 of 40 smbus/i 2 c serial interface control of the adt74 70 is carri ed out using the serial system m anagement bus (smbus). this interface is fully compatible with smbus 2.0 electrical spec ification s and meets 400 pf bus capacitance requirem ents. the device also supports f ast i 2 c (400 khz max). the adt7470 is con nect ed to the bus as a slave device under the control of a master controller or service processor. address selection the adt7470 has a 7 - bit serial bus address. when the device is powered up with p in 11 (a ddr) high, the adt7470 has an smbus address of 010 1111 or 0x5e (left - justified). because the address is 7 bits, it can be left - or right - j ustified; this determines whether the address reads as 0x5x or 0x2x. pin 11 can be left floating or tied low for other addressing options , as shown in table 5 . see also figure 4 , figure 5 , and figure 6 . table 5 . adt7470 address select mode pin 11 (addr) state address high (10 k? to v cc ) 010 111 1 (0x5e left - justified or 0x2f right - justified) low (10 k? to gnd) 010 1100 (0x58 left - justified or 0x2c right - justified) floating (no pull - up) 010 11 10 (0x5 c left - justified or 0x2 e right - justified) v cc 10k ? typ addr 04684-0-004 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 adt7470 figure 4 . smbus address = 0x5e or 0x2 f (pin 11 = 1) addr 10k? typ 04684-0-005 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 adt7470 figure 5 . smbus address = 0x5 8 or 0 x2 c (pin 11 = 0) addr 04684-0-006 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 adt7470 figure 6 . smbus address = 0x5c or 0 x 2 e (pin 11 = floating) the device address i s sampled and latched on the first valid smbus transaction, so any additional attempted address ing changes have no immediate effect. the facility to make hardwired changes to the smbus slave address allows the user to avoid conflicts with other devices sharing the same serial bus, for example , if more than one adt7470 is used in a system. serial bus protocol the serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high - to - low transition on the serial data line , sda , while the s erial clock line , scl , remains high. this indicates that an address/data stream follow s. all slave peripherals connected to the serial bus respond to the start condition, and shift in the next 8 bits, consist - ing of a 7 - bit address (msb first) and a n r/ w bit. this determines the direction of the data transfer, that is, whether data is written to or read from the slave device. the peripheral whose address corresponds to the transmit - ted address responds by pulling the data line low du ring the low period before the 9 th clock pulse, known as the acknowledge bit. all other devices o n the bus now remain idle while the selected device waits for data to be read f rom or written to it. if the r/ w bit is 0 , the master wri te s to the slave device. if the r/ w bit is 1 , the master read s from the slave device. 2. data is sent over the serial bus in sequences of 9 clock pulses : 8 bits of data followed by an acknowledge bit from the slave device. transitions o n the data line must occur during the low period of the clock signal and remain stable d uring the high period. this is because a low - to - high transition when the clock is high might be interpreted as a stop signal. the number of data bytes that can be trans mitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 3. after all data bytes are read or written, stop conditions are established. in write m ode, the master pull s the data line high d uring the 10th clock pulse to assert a stop condition. in read m ode, the master device override s the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. this is known as no acknowledge. the master then take s th e data line low
adt7470 data sheet rev. e | page 10 of 40 during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation. however, it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and subsequently cannot be changed without starting a new operation. in the adt7470, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. then data can be written into that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this is illustrated in figure 7. the device address is sent over the bus followed by r/ w set to 0. this is followed by two data bytes. 04684-0-007 1 00 1 1 1 a1 a0 r/w 99 1 1 d7 d6 d5 d4 d3 d2 d1 d0 9 d7 d6 d5 d4 d3 d2 d1 d0 scl sd a scl (continued) sda (continued) start by master ack. by adt7470 ack. by adt7470 ack. by adt7470 stop by master frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte figure 7. writing a register address to the address pointer register, then writing data to the selected register scl sd a 1 01 01 1a1a0 start by master frame 1 serial bus address byte frame 2 address pointer register byte stop by master ack. by adt7470 ack. by adt7470 r/w d7 d6 d5 d4 d3 d2 d1 d0 99 1 04684-0-008 figure 8. writing to the address pointer register only 04684-0-009 scl sd a 1 01 01 1a1a0 start by master frame 1 serial bus address byte frame 2 data byte from adt7470 stop by master ack. by adt7470 no ack. by master r/w d7 d6 d5 d4 d3 d2 d1 d0 99 1 figure 9. reading data from a previously selected register
data sheet adt7470 rev. e | page 11 of 40 the first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. the second data byte is the data to be written to the internal data register. how data is read from a regist er depends on whether or not the address pointer register value is known. if the adt7470 address pointer register value is unknown or not the desired value, it is first necessary to set it to the correct value before data ca n be read from the desired dat a register. this is done by performing a write to the adt7470 as before, but only the data byte containing the register address is sent, because data cannot be written to the register. this is shown in figure 8 . a read operation is then performed consisting of the serial bus address, r/ w bit set to 1, followed by the data byte read from the data register. this is shown in figure 9 . if the address pointer register is kn own to be alre ady at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, so the operation shown in figure 8 can be omitted. note the following: ? although it is possib le to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value, it is not possible to write data to a register without writing to the address pointer r egiste r. this is because the first data byte of a write is always written to the address pointer register. ? in figure 7 to figure 9 , the serial bus address is shown as the default value 01011(a1)(a0), where a1 a nd a0 are set by the address select mode function previously defined. ? in addition to supporting the send byte and receive byte protocols, the adt7470 also supports the read byte protocol . s ee system management bus s pecifications rev. 2.0 for more informat ion . ? if it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. write operations the smbus specification defines several protocols for diff erent types of read and write operations. th e protocols used in the adt7470 are discussed in the following sections . the following abbreviations are used in the diagrams: s start p stop r read w write a acknowledge a no acknowledge the adt7470 uses the following smbus write protocols . send byte in this protocol, the master device sends a single command byte to a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address foll owed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda , and the transaction ends. for the adt7470, the send byte protocol is us ed to write a register address to ram for a subsequent single byte read from the s ame address. this is shown in figure 10. 1 2 3 4 5 6 s w a a p slave address register address 04684-0-010 figure 10 . setting a register address for subsequent read if it is required to read data from the register immediately after setting up the address, the master can assert a repeat start con - dition immediately after the f inal ack and carry out a single - byte read without asserting an intermediate stop condition. write byte in this oper ation , the master device sends a command byte and one data byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device assert s ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda to end the transaction. thi s is shown in figure 1 1 . 1 2 3 4 5 6 7 8 s w a a a p data slave address register address 04684-0-011 figure 11 . single - byte write to a register
adt7470 data sheet rev. e | page 12 of 40 read operations the adt7470 uses the following smbus read protocols . receive byte this is useful when repeatedly reading a single register. the register address must be set up pre viously. in this operation , the master device receives a single byte from a slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. in the adt7470, the receive byte protocol is used to read a single byte of data f rom a register wh ose address was previously set by a send byte or write byte operation. 1 2 3 4 5 6 s r a data a p slave address 04684-0-012 figure 12 . single - byte write from a register alert response address alert response address (ara) is a feature of smbus devices, which allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the smbalert output can be used as an interrupt output or can be used as an smbalert . one or more outputs can be connected to a common smbalert line conne cted to the master. if a device s smbalert line g oes low, the following occurs: 1. smbalert is pulled low. 2. the m aster initiates a read operation and sends the ale rt response address (ara = 000 1100). this is a general call address that must not be used as a specific device address. 3. the device whose smbalert output is low responds to the alert response address, and the master reads its device address. the address of the device is now known , and it can be interrogated in the usual way. 4. if more than one device s smbalert output is low, the one with the lowest device address has priority, in accordance with normal smbus ar bitration. 5. once the adt7470 responds to the alert response address, the master must read the status registers , and the smbalert is cleared only if the error con dition is gone . smb us timeout the adt7470 includes an smbus t imeout fea ture. if there is no smbus activity for more than 31 ms, the adt7470 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the smbus expecting data. some smbus contr ollers cannot handle the smbus t imeout feat ure , so it can be disabled. table 6 . configuration register 1 register 0 x 40 bit address and value description bit 3 todis = 0 smbus timeout e nabled (default). bit 3 todis = 1 smbus timeout d isabled . a lthough the ad t7470 supports packet error checking (pec), its use is optional. it is triggered by supplying the extra clock for the pec byte. the pec byte is calculated using crc - 8. the frame check sequence (fcs) conforms to crc - 8 by the following polynomial: c(x) = x 8 + x 2 + x 1 + 1 consult the smbus 1.1 spec ification for more information by searching online.
data sheet adt7470 rev. e | page 13 of 40 temperature measurem ent using tmp05/ tmp 06 measuring temperatur e the adt7470 can be connected with up to 10 daisy - chained tmp05/ tmp 06 devices for temperature measurement. each tmp05/ tmp 06 performs an ambient temperature measure - ment, and outputs a pwm signal. the adt7470 decodes the pwm into a temperature measurement, and stores the result in the temperature reading registers, listed in table 7 . the ma ximum temperature read back from all tmp05 temperature readings is stored in register 0x78. to use the adt7470 with tmp05/ tmp 06, the parts should be connected as shown in figure 13 . pin 13 on the adt7470 should be configured as tmp _ sta rt, by s e tting configuration register 1 b it 7 to bit 1. (register address 0x40 bit [7] =1). the start pulse required by the tmp05/06 will be output on the tmp_start pin. the out pin on the last tmp05/06 in the dais y - chain should be connected to p in 12 o n the adt7470, tmp_in. for more information on the tmp05/06 , refer to the tmp05/ tmp 06 data sheet. reporting of 8 - bit temperature val ues occurs only if th e tmp_in function is used and if tmp05/tmp06s are daisy - chaine d according to their data sheet and conne cted as shown . the adt7470 does not have any temperature measurement capability when used as a stand alone device without tmp05s and tmp06s connected. table 7 . temperature reading registers register reading default 0x20 temperatur e 1 reading 0x00 0x21 temperature 2 reading 0x00 0x22 temperature 3 reading 0x00 0x23 temperature 4 reading 0x00 0x24 temperature 5 reading 0x00 0x25 temperature 6 reading 0x00 0x26 temperature 7 reading 0x00 0x27 temperature 8 reading 0x00 0x28 te mperature 9 reading 0x00 0x29 temperature 10 reading 0x00 0x78 max tmp05 temperature 0x00 tmp05/ tmp 06 decoder the adt7470 includes a pwm processing engi ne to decode the daisy - chained pwm output from multiple tmp05s and tmp06s. it then passes each decode d temperature value to the temper - ature value register s. this allows the adt7470 to do high/ low limit comparisons of temperature and to automatically control fan speed based on measured temperature. the pwm processing engine contains all necessary logic t o initiate start conversions on the first daisy - chained tmp05/ tmp 06 and to synchronize with each temperature value as it is fed back to the device through the daisy chain. the start function is multi - plexed on to the same pin that can be used to blast the fans to full speed. the start conversion for tmp05/ tmp 06 temp - erature measurement is fully tr ansparent to the user and does not require any software intervention to function. no. 1 conv/in out no. 2 conv/in out no. 3 no. n conv/in out conv/in out 04684-0-013 tmp05/ tmp06 tmp05/ tmp06 tmp05/ tmp06 tmp05/ tmp06 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 gnd v cc tach3 tach2 tach1 pwm2 scl pwm1 smbalert pwm4 pwm3 tach4 addr tmp_in sda adt7470 full_speed/tmp_start figure 13 . interfacing the ad t7470 to multiple daisy - chained tmp05/ tmp 06 temperature sensor s
adt7470 data sheet rev. e | page 14 of 40 temperature read back by the host th e user cannot read the adt7470 temperature register values if the adt7470 is in the process of a temperature measurement. the user must wait until the data from all the tmp05s and tmp06s in the chain are received by the adt7470 before reading these values. otherwise, the temperature registers may store an incorrect value. it is recommended to wait at least 200 ms for each tmp05 and tmp06 in the chain. the recommended procedur e is as follows: 1. set register 40 bit[7] = 1. this start s the temperature measurements. 2. wait 200 ms for each tmp05/tmp06 in the loop . 3. set register 40 bit[7] = 0 . 4. read the temperature registers. temperature data for mat temperature data on the adt7470 is sto red in an 8 - bit format, with the 7 lsbs being the temperature, and the msb acting as the sign bit. use the following formulae when reading back from the temperature registers, o calculate the temperature: positive temperature = adc code (d ecimal ) negative temperature = adc (decimal) minus 256 for negative temperature readings, the msb is always set to 1. example: 1. temperature read back from register 0x20: 0xff . 2. convert into decimal format. 0xff = 255 (decimal). 3. check if msb is set to 1. it is in this exam ple. therefore , use negative temperature formula, adc (d) minus 256 . 4. temperature = 255 ? 256 = ? 1 c. table 8 . temperature data format temperature ( c) digital output (8 bit) ? 128 1000 0000 ? 125 1000 0011 ? 100 1001 1100 ? 75 1011 0101 ? 50 1100 1110 ? 25 1110 0111 ? 10 1111 0110 + 0 0000 0000 + 10 0000 1010 + 25 0001 1001 + 50 0011 0010 + 75 0100 1011 + 100 0110 0100 + 125 0111 1101 + 175 0111 1111 40ms 40ms 76ms 100ms t start adt7470 t 1 stop t 2 stop tmp_start tmp_in adt7470 tmp05 1 temp = 25 c tmp05 2 temp = 120 c notes: t start is generated by the adt7470 and is the start pulse for tmp05 1. t 1 stop is generated by tmp05 1 and is the start pulse for tmp05 2. t 2 stop is generated by tmp05 2. each start/stop pulse is typically 25 s. tmp05s must be in daisy-chain mode. see the tmp05 data sheet for more information. t 2 t 1 t 1 low t 1 high t 2 low t 2 high 04684-0-032 figure 14 . typical timing diagram of adt7470 with tw o tmp05s connected in daisy - chain mode
data sheet adt7470 rev. e | page 15 of 40 temperature measurem ent limits high and low temperature limits can be individually set for each of the tm p 05/06s that the adt7470 is monitoring. the temperature limit registers are at address 0x44 to 0x57. the powe r - on default value for all tmp05/06 lower limits is ? 127c (0x81). the power C on default value for all tmp05/06 upper limits is +127c (0x7f). see table 9 for details on the temperature limit registers. if the temperature measured from a tmp05/06 exceeds the upper or lower limit, th en a status bit in the interrupt status registers will be set to 1. see table 12 and table 13 for more details on the temperature status bits. smbalert will assert is any temperature exc eeds either the upper or lower limits. the temperature measurements can be masked as interrupt sources for smbalert using the interrupt mask registers, 0x72 and 0x73. see table 14 and tab le 15 for more details on the interrupt mask registers. thermal zones for automatic fan co ntrol the adt7470 can control up to four independent thermal zones with individual fans. the user can configure which tmp05 controls which fan via register 0x7c and 0x7d.for each of the four thermal zones, an individual tmp05, or the hottest tmp05 in the daisy chain, can control the fan. in a system with n tmp05s, it is possible to have 1 or n tmp05s controlling each fan . thermal zone t min for each of the four therm al zones, the user can configure the minimum temperature at which the fans run. registers 0x6e to 0x71 should be configured with the minimum temperature for each thermal zone. when the temperature exceeds t min for that thermal zone, the fans run at minimum speed (pwm min ). the fan speed increases to maximum speed (pwm max ) at [t min + 20c]. fan on/off hysteresis is set at 4 c so that the fans turn off 4 c below the temperature at which they turn on . this prevents fan chatter in the system.
adt7470 data sheet rev. e | page 16 of 40 limit and status re gisters limit values associated with each measurement channel on the adt7470 are high and low limits. these can form the basis of system status monitoring; a status bit can be set for any out - of - limit condition and be detected by polling the device. alt ernatively, smbalert interrupts can be generated to automatically flag a service processor or microcontroller for out - of - limit conditions as they occur. temperature limits table 9 list s the 8 - bit temperature limits on the adt7470. table 9 . temperature limit registers (8 - bit limits) register address description default 0x 44 temperature 1 low limit 0x 81 0x 45 temperature 1 high limit 0x 7f 0x 46 temperature 2 low limit 0x 81 0x 4 7 temperature 2 high limit 0x 7f 0x 48 temperature 3 low limit 0x 81 0x 49 temperature 3 high limit 0x 7f 0x 4a temperature 4 low limit 0x 81 0x 4b temperature 4 high limit 0x 7f 0x 4c temperature 5 low limit 0x 81 0x 4d temperature 5 high lim it 0x 7f 0x 4e temperature 6 low limit 0x 81 0x 4f temperature 6 high limit 0x 7f 0x 50 temperature 7 low limit 0x 81 0x 51 temperature 7 high limit 0x7f 0x 52 temperature 8 low limit 0x 81 0x 53 temperature 8 high limit 0x 7f 0x 54 temperatu re 9 low limit 0x 81 0x 55 temperature 9 high limit 0x 7f 0x 56 temperature 10 low limit 0x 81 0x 57 temperature 10 high limit 0x 7f fan speed limits the f an tach measur ements are 16 - bit results. the f an tach limits are also 16 bits, consisting of two bytes : a high byte and low byte. on the adt7470 it is possible to set both high and low speed fan limits for over speed and under speed or stall con - ditions . be aware that , because the fan tach period is actually being measured, exceeding the limit by 1 indicates a slow or stalled fan. likewise, exceeding the high speed lim it by 1 generates an over speed condition. table 10. fan underspeed limit registers register address description default 0x 58 tach 1 min low byte 0x ff 0 x 59 tach 1 min high byte 0x ff 0x 5a tach 2 min low byte 0x ff 0x 5b tach 2 min high byte 0x ff 0x 5c tach 3 min low byte 0x ff 0x 5d tach 3 min high byte 0x ff 0x 5e tach 4 min low byte 0x ff 0x 5f tach 4 min high byte 0x ff table 11. fan overspeed limit registers register address description default 0x 60 tach 1 max low byte 0x 00 0x 61 tach 1 max high byte 0x 00 0x 62 tach 2 max low byte 0x 00 0x 63 tach 2 max high byte 0x 00 0x 64 tach 3 max low byte 0x 00 0x 65 tach 3 max high byte 0x 00 0x 66 tach 4 max low byte 0x 00 0x 67 tach 4 max high byte 0x 00 out - of - limit comparisons once all limits are programmed, the adt7470 can be enab led to begin monitoring. the adt7470 measure s all parameters in round - robin format and sets the appropriate s tatus bit for out - of - limit conditions. comparisons are done differently depending on whether the measured value is compared to a high limit or a low limit. high limit: > comparison performed low limit: comparison performed
data sheet adt7470 rev. e | page 17 of 40 status registers the results of limit comparison s are stored in status register 1 and status register 2. the status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. if a measurement is within limits , the corre - sponding status register bit is cleared to 0. if the measurement is out of limit, the correspo nding status register bit is set to 1 . the state of the various measurement channels can be polled by reading the statu s registers over the serial bus. when bit 7 (ool) of status re gister 1 (register 0x41) is a 1, an out - of - limit event has been flagged in status register 2. this means that status register 2 must be read only when the ool bit is set. reading the s tatus reg isters clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. stat us register bits are sticky . whenever a status bit is set, indicating an out - of - limit condition, it remain s set even if the event that caused it has gone away (until read). the only way to clear the status bit is to read the status register when the event has gone away. interrupt status mask registers (register 0x72 and register 0x73) allow individual interrupt sources to be masked from causing an smbalert . however, if one of these masked interrupt sources goes out of limit, its associated status bit is still set in the interrupt status registers. this allows the device to be periodically polled to determine if an error co ndition has subsided, without unnecessarily tying up precious system resources handling interrupt service routines. the issue is that the device could potentially interrupt the system every monitoring cycle ( < 1 sec) as long as a measurement parameter rema ins out of limit. masking eliminates unwanted system interrupts. the ool bit (r egister 0x41 bit [7]), and the norm bi t (r egister 0x42 bit [3]) do not activate smbalert . table 12. interrupt status register 1 (register 0x41) bit no. mnemonic description 7 ool a 1 d enotes that a bit in status register 2 is set and status register 2 should now be read. 6 r7t a 1 i ndicates that tmp05 temperature 7 high or low limit has been exceeded. 5 r6t a 1 i ndicates that t mp05 temperature 6 high or low limit has been exceeded. 4 r5t a 1 i ndicates that tmp05 temperature 5 high or low limit has been exceeded. 3 r4t a 1 i ndicates that tmp05 temperature 4 high or low limit has been exceeded. 2 r3t a 1 i ndicates that tmp05 te mperature 3 high or low limit has been exceeded. 1 r2t a 1 i ndicates that tmp05 temperature 2 high or low limit has been exceeded. 0 r1t a 1 i ndicates that tmp05 temperature 1 high or low limit has been exceeded. table 13. inter rupt status register 2 (register 0x42) bit no. mnemonic description 7 fan 4 a 1 i ndicates that fan 4 has dropped below minimum speed or is above maximum speed. 6 fan 3 a 1 i ndicates that fan 3 has dropped below minimum speed or is above maximum speed. 5 fan 2 a 1 i ndicates that fan 2 has dropped below minimum speed or is above maximum speed. 4 fan 1 a 1 i ndicates that fan 1 has dropped below minimum speed or is above maximum speed. 3 norm a 1 i ndicates that the temperatures are below t min and that the fans are supposed to be off. 2 r10t a 1 i ndicates that tmp05 temperature 10 high or low limit has been exceeded. 1 r9 t a 1 i ndicates that tmp05 temperature 9 high or low limit has been exceeded. 0 r8t a 1 i ndicates that tmp05 temperature 8 high or low limit has been exceeded.
adt7470 data sheet rev. e | page 18 of 40 smbalert interrupt the adt7470 can be polled for status, or an smbalert interrupt can be generated for out-of-limit conditions. note how the smbalert output and status bits behave when writing interrupt handler software. figure 15 shows how the smbalert output and sticky status bits behave. once a limit is exceeded, the corresponding status bit is set to 1. the status bit remains set until the error condition subsides the status register is read. the status bits are referred to as sticky because they remain set until read by software. this ensures that an out-of-limit event cannot be missed if software is polling the device periodically. the smbalert output remains low for the duration that a reading is out of limit until the status register is read. this has implications for how software handles the interrupt. handling smbalert interrupts to prevent the system from being tied up servicing interrupts, handle the smbalert interrupt as follows: 1. detect the smbalert assertion. 2. enter the interrupt handler. 3. read the status registers to identify the interrupt source. 4. mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (register 0x72 and register 0x73). 5. take the appropriate action for a given interrupt source. 6. exit the interrupt handler. 7. periodically poll the status registers. if the interrupt status bit is cleared, reset the corresponding interrupt mask bit to 0. this causes the smbalert output and status bits to behave as shown in figure 16. "sticky" status bit high limit t emperatur e smbalert cleared on read (temp below limit) temp back in limit (status bit stays set) 04684-0-020 figure 15. smbalert and status bit behavior "sticky" status bit high limit temperature smbalert cleared on read (temp below limit) temp back in limit (status bit stays set) interrupt mask bit set interrupt mask bit cleared (smbalert re-enabled) 04684-0-021 figure 16. how masking the interrupt source affects smbalert output
data sheet adt7470 rev. e | page 19 of 40 masking interrupt sources interrupt mask re gister 1 and interrupt mask re gister 2 are located at address 0x72 and address 0x73. these allow indi - vidual interrupt sources to be masked out to prevent unwanted smbalert interrupts. m asking an interrupt source prevents only the smbalert output from being asserted; the appro - priate status bit is still set as usual . this is useful if the system polls the monitoring devices periodically to determine whether or not out - of - limit conditions have subsided, wi thout tying up time - critical system resources. enabling the smbalert interrupt output the smbalert interrupt output is a dedicate d function pro - vided on p in 14 to signal out - of - limit conditions to a host or sys tem pro cessor. because this is a dedicated function, it is important that limit registers be programmed before monitoring is enabled to prevent spurious interrupts from occurring on the smbalert pin. although the smbalert output cannot be specifically disabled, interrupt sources can be masked to prevent smbalert assertions. monitoring is enabled when bit 0 (strt) o f configuration register 1 (register 0x40) is set to 1. table 14. interrupt mask register 1 (reg ister 0x72) bit no. mnemonic description 7 unused unused . 6 r7t a 1 m asks the smbalert for tmp05 temperature 7. 5 r6t a 1 m asks the smbalert for tmp05 temperatur e 6. 4 r5t a 1 m asks the smbalert for tmp05 temperature 5. 3 r4t a 1 m asks the smbalert for tmp05 temperature 4. 2 r3t a 1 m asks the smbalert for tmp05 temperature 3. 1 r2t a 1 m asks the smbalert for tmp05 temperature 2. 0 r1t a 1 m asks the smbalert for tmp05 temperature 1. table 15. interrupt mask register 2 (r egister 0x73) bit no. mnemonic description 7 fan 4 a 1 m asks the smbalert for fan 4 overspeed/ underspeed conditions. 6 fan 3 a 1 m asks the smbalert for fan 3 overspeed/ underspeed conditions. 5 fan 2 a 1 m asks the smbalert for fan 2 over speed/ underspeed conditions. 4 fan 1 a 1 m asks the smbalert for fan 1 overspeed/ underspeed conditions. 3 unused unused . 2 r10t a 1 m asks the smbalert for tmp05 temperature 10. 1 r9t a 1 m asks the smbalert for tmp05 temperature 9. 0 r8t a 1 m asks the smbalert for tmp05 temperature 8.
adt7470 data sheet rev. e | page 20 of 40 fan drive using pwm control the adt7470 uses pulse - width modulation (pwm) to control fan speed. this relies on varying the dut y cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. t wo main control schemes are used: low frequency and high fre - quency pwm. configuration register 1 bit [6], at address 0x40, configures the fan drive for high or low freque ncy operation. if this bit is set to 0, which is the default, high frequency fan drive is selected. if this bit is set to 1, low frequency fan drive is selected. all four pwm outputs on the adt7470 have the same drive frequency. high frequency fan d rive on e of the important features of fan controllers is t he pwm drive frequency. m ost fans are driven asynchronously at low frequency (30 hz to 100 hz). increasingly , the devices drive fans at greater than 20 khz. these controllers are meant to drive 4 - wire fan s with pwm c ontrol built - in internal to the fan in figure 17. t he adt7470 supports high frequency pwm ( great than 20 khz) , as well as 1.4 khz and other low frequency pwm . this allows the user to drive 3 - wire or 4 - wire fans. if usi ng 3 - wire fans this mode, care should be taken to ensure that incomplete tach information does not occur at low pwm duty cycles, or short pwm pulse widths. v pwm 3.3v 10k? tach adt7470 12v 10k? tach 10k? 4.7k? 1n4148 04684-0-024 gnd pwm_in figure 17 . driving a 4 - wire fan low frequency fan dr ive for low frequen cy, low - side drive, the external circuitry required to drive a fan using pwm control is extremely simple. a single nmos fet is the only drive device required. the spec ifications of the mosfet depend on the maximum current required by the fan being driven. typical notebook fans draw a nominal 170 ma; therefore, sot devices can be used where board space is a concern. in desktops, fans can typically draw 250 ma to 300 ma each. if the user needs to drive several fans in parallel from a single pwm output or driv e larg er server fans, the mosfet need s to handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, vgs , less than 3.3 v, for d irect interfacing to the pwm pin of the adt7470 . vgs of the chosen mosfet can be greater than 3.3 v as long as the pull - up on its gate is tied to 5 v. the m osfet should also have a low on resistance to ensure that there is not significant voltage drop across the fet. this would reduce the voltage applied across the fan a nd, therefore, the maximum operating speed of the fan. figure 18 shows how a 3 - wire fan can be driven using low frequency pwm control where the control method is low - side, low frequency switching. figure 1 8 shows the ideal interface when interfacing a tach signal from a 12 v fan (or greater voltage) to a 5 v (or less) logic device. in all cases, the tach signal from the fan must be kept below 5 v maximum to prevent damage to the adt7470. the three resistor s in figure 18 ensure that the tach voltage is kept within safe levels for typical desktop and notebook systems. 12v q1 ndt3055l pwm 3.3v 10k ? 12v fan tach/ain adt7470 12v 10k ? tach 10k ? 4.7k ? 1n4148 04684-0-022 figure 18 . driving a 3 - wire fan using an n - channel mosfet
data sheet adt7470 rev. e | page 21 of 40 figur e 19 shows a fan drive circuit using an npn transistor such as a general - purpose mmbt2222. while these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than mosfets. when choosing a tra nsistor, care should be taken to ensure that it meets the fans current requirements. this is the only major difference between a mosfet and npn transistor fan driver circuit. when using transistors, ensure that the base resistor is chosen such that the transisto r is fully saturated when the fan is powered on. otherwise, there are power inefficiencies in the implementation. 12v q1 mmbt2222 pwm 3.3v 470 ? 12v fan tach/ain adt7470 12v 10k ? tach 10k ? 4.7k ? 1n4148 04684-0-023 figure 19 . driving a 3 - wire fan using an npn transistor low f requency setting the fan driv e frequency configurati on register 2 bit s[6:4] configure the fan drive frequency in both high and low frequency drive mode. table 16. fan drive frequency register 0x74[6:4] high frequency drive (0x40[6] = 0) low frequency drive (0x40[6] = 1) 000 1.4 kh z 11 hz 001 22.5 khz 14.7 hz 010 22.5 khz 22.1 hz 011 22.5 khz 29.4 hz 100 22.5 khz 35.3 hz 101 22.5 khz 44.1 hz 110 22.5 khz 58.8 hz 111 22.5 khz 88.2 hz inverted pwm output the pwm duty cycle can be inverted by writing to the pwm configuration r egisters. if the pwm duty cycle is inverted, then a pwm duty cycle setting of 33% results in an output duty cycle of 66%, as the pwm waveform is inverted. table 17. pwm1/ pwm 2 configuration ( register 0x68) bit no. mnemonic descriptio n 5 inv1 0 = pwm1 duty cycle not inverted (default) . 1 = pwm1 duty cycle inverted. 4 inv2 0 = pwm2 duty cycle not inverted (default) . 1 = pwm2 duty cycle inverted. table 18. pwm3/ pwm 4 configuration ( register 0x69 ) bit no. mnemo nic description 5 inv3 0 = pwm3 duty cycle not inverted (default) . 1 = pwm3 duty cycle inverted. 4 inv4 0 = pwm4 duty cycle not inverted (default) . 1 = pwm4 duty cycle inverted. fan full speed funct ion when p in 13 is configured for full speed operati on, pulling the pin low will cause all fans to run at the maximum pwm duty cycle. a l ogic 1 is output on the pwm pins in this case.
adt7470 data sheet rev. e | page 22 of 40 fan speed measurement tach inputs pin 6, pin 7, pin 4, and pin 9 are open-drain tach inputs intended for fan speed measurement. signal conditioning in the adt7470 accommodates the slow rise and fall times typical of fan tachometer outputs. the maxi- mum input signal range is 0 v to 5 v, even where v cc is less than 5 v. if these inputs are supplied from fan outputs that exceed 0 v to 5 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 20 to figure 23 show circuits for most common fan tach outputs. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in figure 20. 12v fan speed counter tach pullup 4.7k? typ tach output v cc adt7470 04684-0-025 figure 20. fan with tach pull-up to v cc if the fan output has a resistive pull-up to 12 v (or other voltage greater than 5 v), the fan output can be clamped with a zener diode, as shown in figure 21. the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 5 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 5 v is suitable. 12v fan speed counter tach tach output zd1* zener pullup 4.7k ? typ *choose zd1 voltage approx. 0.8 ? v cc v cc adt7470 04684-0-026 figure 21. fan with tach. pull-up to voltage > 5 v, for example, 12 v clamped with zener diode. if the fan output has a resistive pull-up to 12 v (or other voltage greater than 5 v), the fan output can be clamped with a zener diode, as shown in figure 21. the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 5 v, allowing for the voltage tolerance of the zener. a value of between 3 v and 5 v is suitable. if the fan has a strong pull-up (less than 1 k) to 12 v, or a totem-pole output, a series resistor can be added to limit the zener current, as shown in figure 22. alternatively, a resistive attenuator can be used, as shown in figure 23. r1 and r2 should be chosen such that 2 v < v pull-up r2 /( r pull-up + r1 + r2 ) < 5 v the fan inputs have an input resistance of nominally 160 k to ground, which should be taken into account when calculating resistor values. with a pull-up voltage of 12 v and pull-up resistor less than 1 k, suitable values for r1 and r2 are 100 k and 47 k. this gives a high input voltage of 3.83 v. 12v fan speed counter tach pullup typ. <1k ? or totem-pole zd1 zener* r1 10k ? tach o/p *choose zd1 voltage approx. 0.8 ? v cc v cc adt7470 04684-0-027 figure 22. fan with strong tach. pull-up to > v cc or totem-pole output, clamped with zener and resistor. 12v fan speed counter tach tach output r1* r2* <1k ? v cc *see text adt7470 04684-0-028 figure 23. fan with strong tach. pull-up to > v cc or totem-pole output, attenuated with r1/r2. pulse stretching pulse stretching of the pwm output is performed automatically in low frequency fan drive mode, to ensure that sufficient tach readings are taken from the fan. however, in high frequency fan drive mode, pulse stretching is disabled. if using 3-wire fans this mode, care should be taken to ensure that incomplete tach information does not occur at low pwm duty cycles, or short pwm pulse widths. disabling tach measurement the tach measurement for each fan can be disabled by writing to configuration register 2 bits[3:0], at address 0x74.
data sheet adt7470 rev. e | page 23 of 40 fan speed measurement the fan counter does not count the fan tach output pulses directly, because the fan speed may be less than 1000 rpm, and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is measured by gating an on-chip 90 khz oscillator into the input of a 16-bit counter for n periods of the fan tach output, as shown in figure 24, so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. n, the number of pulses counted, is determined by the settings of register 0x43 (fan pulses per revolution register). this register contains two bits for each fan, allowing 1, 2 (default), 3, or 4 tach pulses to be counted. c lock pwm tach 1 2 3 4 04684-0-029 figure 24. fan speed measurement fan speed measurement registers the fan tachometer readings are 16-bit values consisting of a 2-byte read from the adt7470. table 19. fan speed measurement registers register address description default 0x2a tach 1 low byte 0x00 0x2b tach 1 high byte 0x00 0x2c tach 2 low byte 0x00 0x2d tach 2 high byte 0x00 0x2e tach 3 low byte 0x00 0x2f tach 3 high byte 0x00 0x30 tach 4 low byte 0x00 0x31 tach 4 high byte 0x00 reading fan speed from the adt7470 measuring fan speed involves a 2-register read for each meas- urement. the low byte should be read first. this causes the high byte to be frozen until both high and low byte registers are read from, preventing erroneous tach readings. the fan tachometer reading registers report back the number of 11.11 ms period clocks (90 khz oscillator) gated to the fan speed counter, from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (assuming 2 pulses per revolution are being counted). since the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actually running. a 16-bit fan tachometer reading of 0xffff indicates either that the fan has stalled or is running very slowly (<100 rpm). fan tach limit registers the fan tach limit registers are 16-bit values consisting of two bytes. minimum limits determine fan under speed settings, while maximum limits determine fan over speed settings. table 20. fan tach limit registers register address description default 0x58 tach 1 min low byte 0xff 0x59 tach 1 min high byte 0xff 0x5a tach 2 min low byte 0xff 0x5b tach 2 min high byte 0xff 0x5c tach 3 min low byte 0xff 0x5d tach 3 min high byte 0xff 0x5e tach 4 min low byte 0xff 0x5f tach 4 min high byte 0xff 0x60 tach 1 max low byte 0x00 0x61 tach 1 max high byte 0x00 0x62 tach 2 max low byte 0x00 0x63 tach 2 max high byte 0x00 0x64 tach 3 max low byte 0x00 0x65 tach 3 max high byte 0x00 0x66 tach 4 max low byte 0x00 0x67 tach 4 max high byte 0x00 high limit: comparison because the actual fan tach period is being measured, exceeding a fan tach limit by 1 sets the appropriate status bit and can be used to generate an smbalert. fan speed measurement rate the fan tach readings are updated once every second by default. the fast tach bit (register 0x40 bit[5]) controls the frequency of tach measurements. setting this bit to 1 increases the tach measurements from one per second, to one every 250 ms.
adt7470 data sheet rev. e | page 24 of 40 calculating fan speed and tachometer limits as suming that the measured number of tach pulses per rotation corresponds to the number of pulses counted as set in register 0x43, f an speed is calculated by fan speed (rpm) = (90,000 60) / fan tach reading where fan tach reading is the 16- bit fan tachometer reading . for e xample : tach 1 high byte (reg 0x2b) = 0x17 tach 1 low byte (reg 0x2a) = 0xff what is fan 1 speed in rpm? fan 1 tach reading = 0x17ff = 6143 decimal rpm = (f 60)/fan 1 tach reading rpm = (90000 60)/6143 fan speed = 879 rpm calculat e the tachometer max imum and min imum limits at 1000 rpm and 500 rpm as follows : 1000 rpm (90 ,000 60)/1000 = 5400 decimal 5400 decimal = 1518 h ex tach 1 maximum = 1518 500 rpm (90 ,000 60)/500 = 10800 decimal 10800 decimal = 2a30 h ex tach 1 minimum = 2a30 fan pulses per revolution different fan models can output either 1, 2, 3 , or 4 t ach pulses per revolution. the number of tach pulses per rotation for each fan should be programm ed in to the fan pulses per revolution regist er (register 0x43). if a n incorrect value is programmed , then the fan speed cannot be determined using the equation in the calculating fan speed section. alternatively, if the number of tach pulses per rotation is not know, this register can be used in determining the number of pulses/revolution output by a given fan. by plotting fan speed measurements at maximum speed with different pulses/ revolution settings, the smoothest graph with the lowest ripple determines the correct pulses/revolution value.
data sheet adt7470 rev. e | page 25 of 40 manual fan speed control manual fan speed control on the adt7470 allows the user to control the pwm duty cycle for each fan via the registers. the ad t 7470 powers - up in manual fan contro l mode, with all pwm duty cycles set to maximum. the pwm configuration registers determine whether the fans are in manual or automatic fan control mode. setting the pwm duty cycle the adt7470 allows the duty cycle of any pwm output to be manually adjuste d . this can be useful if users want to change fan speed in software or want to adjust pwm duty cycle output for test purposes. the pwm current duty cycle regist ers (register 0x32 to register 0x35) can be written with 8 - bit values in manual fan speed contr ol mode to manually adjust the speeds of the cooling fans. the pwm duty cycle for each output can be set anywhere from 0% to 100% , in steps of 0.39%. the value to be programmed into the pwm current duty cycle registers can be calculated as follows: valu e ( decimal ) = desired pwm duty cycle /0.39 example 1: for a pwm duty cycle of 50% value ( decimal ) = 50/0.39 = 128 decimal value = 128 decimal or 80 hex example 2: for a pwm duty cycle of 33% value ( decimal ) = 33/0. 39 = 85 decimal value = 85 decimal or 54 he x table 21. pwm current duty cycle registers register address description default 0x32 pwm1 duty cycle 0xff ( 100% ) 0x33 pwm2 duty cycle 0xff ( 100% ) 0x34 pwm3 duty cycle 0xff ( 100% ) 0x35 pwm4 duty cycle 0xff ( 100% ) tab le 22 .fan control mode configuration register /bit mnenonic description 0x68 bit [6] bhvr2 this bit determines fan behavior for pwm2 output. 0 = manual mode (pwm2 duty cycle controlled in software). 1 = fastest speed calculated by a ll temperatures control pwm2 (automatic fan control mode). 0x68 bit [7] bhvr1 this bit determines fan behavior for pwm1 output. 0 = manual mode (pwm1 duty cycle controlled in software). 1 = fastest speed calculated by all temperatures control pwm1 (automa tic fan control mode). 0x69 bit [6] bhvr4 this bit determines fan behavior for pwm4 output. 0 = manual mode (pwm4 duty cycle controlled in software). 1 = fastest speed calculated by all temperatures control pwm4 (automatic fan control mode). 0x69 bit [7] bhvr3 this bit determines fan behavior for pwm3 output. 0 = manual mode (pwm3 duty cycle controlled in software). 1 = fastest speed calculated by all temperatures control pwm3 (automatic fan control mode).
adt7470 data sheet rev. e | page 26 of 40 automatic fan speed control in automatic fa n speed control mode, fan speed automatically varies with temperature and without cpu intervention, once initial parameters are set up. the advanta ge is that when a system hangs, the user is guaranteed that the system is protected from overheating. automa tic fan speed control mode is recommended for use only when temperatures > 8c. in automatic fan control mode, if the temperature drops below 0c, the fans automatically turn on. for each thermal zone, when the temperature exceeds t min , the fans turn on at pwm min duty cycle. when the temperature reaches t min + 20c, the fans increase in speed to pwm max . to configure each fan into automatic fan control mode, the bhvr bit for th at fan must be set to 1. see table 22 for more details . to control the fans in automatic fan control mode, a number of parameters for each fan should be set up. the pwm minimum and maximum duty cycles, as well as the minimum temperature at which each fan turns on, should be configured. which tmp05 controls w hich fan also needs to be configured. what follows are the a utom atic fan control configuration steps : 1. put the fans into automatic fan control mode, by setting the bhvr bits for each fan to 1. 2. determine which tmp05 is to c ontrol the fan, by configuring r eg isters 0x7c and 0x7d. any tmp05, can control any fan, or the hottest tmp05 can control the fan. 3. set the minimum temperatu re for each fan, by writing to r egisters 0x6e to 0x70. when the temperature exceeds t min , the fan run s at pwm min . 4. set pwm min , the mini mum pwm duty cycle, by writing to r egisters 0x6a to 0x6d. 5. set pwm max , the maximum pwm duty cycle, by writing to registers 0x38 to 0x3b. 6. write to the strt bit in configuration r egister 1 (0x40 bit [0]) to start the adt7470 monitoring cycle. set b it 7 in this register to 1 to enable the tmp05 start pulse. pwm min duty cycle the pwm min duty cycle registers, at address 0x6a to 0x6d, set the pwm duty cycle at which the fans turn on in automatic fan control mode. t he value to be programmed into the pwm min duty cycle registers can be calculated as follows: value ( decimal ) = desired pwm duty cycle /0.39 example : for a pwm min duty cycle of 3 0% value ( decimal ) = 3 0/0.39 = 77 decimal value = 77 decimal or 4d hex the pwm min duty cycle registers have a default value of 0x80, which cor responds to a duty cycle of 50% on the pwm output pin. pwn max duty cycle for each fan, the maximum pwm duty cycle can be set by writing to r egisters 0x38 to 0x3b. the value to be programmed into the pwm max duty cycle registers can be c alculated as follows: value ( decimal ) = desired pwm duty cycle /0.39 example : for a pwm max duty cycle of 9 0% value ( decimal ) = 90/0.39 = 230 decimal value = 230 decimal or e6 hex the pwm max duty cycle registers have a default value of 0xff, which corre spo nds to a logic 1 on the pwm output pin. pwm current duty cycle in automatic fan control mode, the current pwm duty cycle for each fan is recorded in the pwm current duty cycle registers, ( 0x02 to 0x35 ) . by reading t hese registers, the user can keep track o f the current duty cycle on each pwm output . during fan start up, these registers report back 0x00. if the fullspeed pin is activated, to blast the fans to the maximum possible pwm ( logic high), the pwm current duty cycle register is n o t updated.
data sheet adt7470 rev. e | page 27 of 40 register map table 23 . adt7470 register map address r/w description default lockable 0x20 r temperature 1 reading 0x00 0x21 r temperature 2 reading 0x00 0x22 r temperature 3 reading 0x00 0x23 r temperature 4 rea ding 0x00 0x24 r temperature 5 reading 0x00 0x25 r temperature 6 reading 0x00 0x26 r temperature 7 reading 0x00 0x27 r temperature 8 reading 0x00 0x28 r temperature 9 reading 0x00 0x29 r temperature 10 reading 0x00 0x2a r tach 1 low byte 0xff 0x2b r tach 1 high byte 0xff 0x2c r tach 2 low byte 0xff 0x2d r tach 2 high byte 0xff 0x2e r tach 3 low byte 0xff 0x2f r tach 3 high byte 0xff 0x30 r tach 4 low byte 0xff 0x31 r tach 4 high byte 0xff 0x32 r/w pwm1 current duty cycle 0xff 0x33 r/w pwm2 current duty cycle 0xff 0x34 r/w pwm3 current duty cycle 0xff 0x35 r/w pwm4 current duty cycle 0xff 0x36 r reserved 0x00 0x37 r/w adi test register 1 0x00 y 0x38 r/w pwm1 max duty cycle 0xff 0x39 r/w pwm2 max duty cycle 0xff 0x3 a r/w pwm3 max duty cycle 0xff 0x3b r/w pwm4 max duty cycle 0xff 0x3c r/w adi test register 2 0x00 y 0x3d r device id register 0x70 0x3e r company id number 0x41 0x3f r revision number 0x0 2 0x40 r/w configuration register 1 0x01 0x41 r interru pt status register 1 0xxx 0x42 r interrupt status register 2 0xxx 0x43 r/w fan pulses per revolution 0x55 0x44 r/w temperature 1 low limit 0x81 0x45 r/w temperature 1 high limit 0x7f 0x46 r/w temperature 2 low limit 0x81 0x47 r/w temperature 2 high limit 0x7f 0x48 r/w temperature 3 low limit 0x81 0x49 r/w temperature 3 high limit 0x7f 0x4a r/w temperature 4 low limit 0x81 0x4b r/w temperature 4 high limit 0x7f 0x4c r/w temperature 5 low limit 0x81 0x4d r/w temperature 5 high limit 0x 7f 0x4e r/w temperature 6 low limit 0x81 0x4f r/w temperature 6 high limit 0x7f 0x50 r/w temperature 7 low limit 0x81 0x51 r/w temperature 7 high limit 0x7f 0x52 r/w temperature 8 low limit 0x81 0x53 r/w temperature 8 high limit 0x7f
adt7470 data sheet rev. e | page 28 of 40 address r/w description default lockable 0x54 r/w temperature 9 low limit 0x81 0x55 r/w temperature 9 high limit 0x7f 0x56 r/w temperature 10 low limit 0x81 0x57 r/w temperature 10 high limit 0x7f 0x58 r/w tach 1 min low byte 0xff 0x59 r/w tach 1 min high byte 0xff 0x5a r/w tach 2 min low byt e 0xff 0x5b r/w tach 2 min high byte 0xff 0x5c r/w tach 3 min low byte 0xff 0x5d r/w tach 3 min high byte 0xff 0x5e r/w tach 4 min low byte 0xff 0x5f r/w tach 4 min high byte 0xff 0x60 r/w tach 1 max low byte 0x00 0x61 r/w tach 1 max high byt e 0x00 0x62 r/w tach 2 max low byte 0x00 0x63 r/w tach 2 max high byte 0x00 0x64 r/w tach 3 max low byte 0x00 0x65 r/w tach 3 max high byte 0x00 0x66 r/w tach 4 max low byte 0x00 0x67 r/w tach 4 max high byte 0x00 0x68 r/w pwm1/2 config regis ter 0x00 y 0x69 r/w pwm3/4 config register 0x00 y 0x6a r/w pwm1 min duty cycle 0x80 y 0x6b r/w pwm2 min duty cycle 0x80 y 0x6c r/w pwm3 min duty cycle 0x80 y 0x6d r/w pwm4 min duty cycle 0x80 y 0x6e r/w temperature 1 t min 0x5a 0x6f r/w temperature 2 t min 0x5a 0x70 r/w temperature 3 t min 0x5a 0x71 r/w temperature 4 t min 0x5a 0x72 r/w interrupt mask 1 register 0x00 0x73 r/w interrupt mask 2 register 0x00 0x74 r/w configuration register 2 0x00 0x75 r/w reserved. do not write to this registe r. 0x00 0x76 r/w reserved. do not write to this register. 0x00 0x77 r/w adi test register 3 0x00 y 0x78 r max tmp05 temperature 0x00 0x79 r/w reserved. do not write to this register. 0x00 0x7a r/w reserved. do not write to this register. 0x00 0x 7b r/w reserved. do not write to this register. 0x00 0x7c r/w tmp05 zone select 1 0x00 0x7d r/w tmp05 zone select 2 0x00 0x7e r/w reserved. do not write to this register. 0x00 0x7f r/w gpio enable 0x00 0x80 r/w gpio config 0x00 0x81 r gpio stat us 0x00
data sheet adt7470 rev. e | page 29 of 40 detailed register de scriptions table 24. register 0x20 to register 0x29. tempe rature reading registers (power - on default = 0x00) . register address read/write description comments 0x20 read - only 8 - bit temperature 1 r eading (from tmp05 sensor) . bit[7] = sign bit, indicates if temperature is positive or 0x21 read - only 8 - bit temperature 2 r eading (from tmp05 sensor) . negative 0x22 read - only 8 - bit temperature 3 r eading (from tmp05 sensor) . bits[6:0] = temperature result 0x23 read - only 8 - bit temperature 4 r eading (from tmp05 sensor) . 0x24 read - only 8 - bit temperature 5 r eading (from tmp05 sensor) . to calculate the temperature: 0x25 read - only 8 - bit temperature 6 r eading (from tmp05 sensor) . positive temperature = adc code (d ecimal ) 0x26 read - only 8 - bit temperature 2 r eading (from tmp05 sensor) . negative temperature = adc (decimal) minus 256 0x27 read - only 8 - bit temperature 3 r eading (from tmp05 sensor) . 0x28 read - only 8 - bit temperature 4 r eading (from tmp05 sensor) . 0x2 9 read - only 8 - bit temperature 5 r eading (from tmp05 sensor) . readings from daisy - chained tmp05 are processed and loaded into the temperature reading registers. table 25. register 0x2a to register 0x31. fa n tach reading registers (power - on default = 0x00 ) . register address read/write description 0x2a read - only tach 1 low byte (8 msbs of reading) . 0x2b read - only tach 1 high byte (8 lsbs of reading) . 0x2c read - only tach 2 high byte (8 msbs of reading) . 0x2d read - only tach 2 low b yte (8 lsbs of reading) . 0x2e read - only tach 3 high byte (8 msbs of reading) . 0x2f read - only tach 3 low byte (8 lsbs of reading) . 0x30 read - only tach 4 high byte (8 msbs of reading) . 0x31 read - only tach 4 low byte (8 lsbs of reading) . the fa n tach rea ding registers shown in table 25 count the number of 11.11 s periods (based on an internal 90 khz clock) that occur between a number of consecutive fan tach pulses (default = 2). the number of tach pulses used to count can be cha nged using the fan pulses per revolution register ( register 0x43). this allows the fan speed to be accurately measured. because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. both the low and high bytes ar e then frozen until read. at power - on, these registers contain 0x0000 until such time as the first valid fan tach measurement is read in to these registers. thi s prevents false interrupts from occurring while the fans are spinning up. a count of 0xffff in dicates that a fan is ? stalled or blocked (object jamming the fan). ? failed (internal circuitry destroyed) . ? not p opulated . t he adt7470 expects to see a fan connected to each tach . if a fan is not connected to that tach , its tach minimum high and l ow byte ar e set to 0xffff. table 26 . register 0x32 to register 0x35 . current pwm duty cycle registers (power - on default = 0xff ) . register address read/write description 0x32 read/write pwm1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff) . 0x33 read/write pwm2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff) . 0x34 read/write pwm3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff) . 0x35 read/write pwm4 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff) . the c urrent pwm duty cycle registers , shown in table 26, reflect the pwm duty cycle driving each fan at any given time. when in automatic fan speed control mode, the adt7470 reports the pwm duty cycles back through these registers . th e pwm duty cycle values va ry according to temperature in a utomatic fan speed control mode. during fan startup, these registers report back 0x00. in manual fan control mode, the pwm duty cycle outputs can be set to any duty cycle value by writing to these r egisters.
adt7470 data sheet rev. e | page 30 of 40 table 27. register 0x38 to register 0x3 b. pwm max duty cycle registers (power - on default = 0xff ) . register address read/write description 0x3 8 read/write pwm1 max duty cycle: pwm1 min duty cycle value (register 0x6a) to 100% duty cycle . 0x3 9 read/write pwm2 max duty cycle : pwm2 min duty cycle value (register 0x6b) to 100% duty cycle . 0x3 a read/write pwm3 max duty cycle : pwm3 min duty cycle value (register 0x6c) to 100% duty cycle . 0x3 b read/write pwm4 max duty cycle : p wm4 min duty cycle value (register 0x6d) to 100% duty cycle . table 28. register 0x3d. device id register (power - on default = 0x70 ) . register address read/write description 0x3d read only device id . the device id register contains the adt7470 d evice id value as a means of identifying the part over the bus. table 29. register 0x3e. company id register (power - on default = 0x41 ) . register address read/write description 0x3e read only company id . the company i d register contains 0x41 , the manufacturer id number representative of the analog devices , inc. product. table 30 . register 0x3f. revision register (power - on default = 0x02 ) . register address read/write description 0x3f read only r evision register . the revision register contains the revision number of the adt7470. table 31. register 0x40. configuration register 1 (power - on default = 0x01 ) . bit name read/write description [ 0 ] strt read/write logic 1 enables monitoring and pwm control outputs based on the limit settings programmed. logic 0 disables monitoring and pwm control based on the default powe r - up limit settings. t he limit values programmed are preserved even if a l ogic 0 is written to this bit and the default settings are enabled. [ 1 ] reserved read/write reserved. write 0 to this bit . [ 2 ] reserved read/write reserved. write 0 to this bit. [ 3 ] todis read/write writing a 1 dis ables smbus timeout. [ 4 ] lock write once once this bit is set, all lockable registers become read - only and cannot be modified until the ad t 7470 is powered down and powered up again. [ 5 ] fst_tch read/write enable fast tach measurement. 0 = tach measurement rate is 1 measurement per second 1= tach measurement rate is 1 measurement every 250ms [ 6 ] hf_lf read/write this bit switches between high frequency and low frequency fan drive. 0 (default) = h igh frequency fan drive (1.4 khz or 22.5 khz. se e configuration register 2, reg ister 0x74 , b its [ 6:4 ] ) in table 44. 1 = low frequency fandrive (frequency determined by configuration register 2, register 0x74, bits [ 6:4 ] ) in table 44. [ 7 ] t05_stb read/write select configuration for p in 13. 0 (default) = full speed input. 1 = tmp05 start pulse output .
data sheet adt7470 rev. e | page 31 of 40 table 32. register 0x 41. int errupt status register 1 (power - on default = 0x00 ) . bit name read/write description [ 0 ] r1t read - only a 1 indicates that the remote 1 temp erature high or low limit has be en exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 1 ] r2t read - only a 1 indicates that the remote 2 temperature high or low limit has been exceeded. this bit is cleared on a read of the status re gister only if the error condition has subsided. [ 2 ] r3t read - only a 1 indicates that the remote 3 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 3 ] r4t re ad - only a 1 indicates that the remote 4 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 4 ] r5t read - only a 1 indicates that the remote 5 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 5 ] r6t read - only a 1 indicates that the remote 6 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 6 ] r7t read - only a 1 indicates that the remote 7 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsi ded. [ 7 ] ool read - only a 1 indicates that an out - of - limit event has been latched in status register 2. this bit is a logical or of all status bits in status register 2. software can test this bit in isolation to determine whether any of the temperature or fan speed readings represent ed by status register 2 are out of limit. this saves the need to read status register 2 every interrupt or polling cycle. table 33. register 0x42. int errupt status register 2 (power - on default = 0x00 ) . bit name read/write description [ 0 ] r8t read - only a 1 indicates that the remote 8 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 1 ] r9t read - only a 1 indi cates that the remote 9 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 2 ] r10t read - only a 1 indicates that the remote 10 temperature high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [ 3 ] norm read - only a 1 indicates that the measured temperatures are normal (below t min ), and the fans should be off. [ 4 ] fan 1 read - only a 1 in dicates that fan 1 has gone above max speed or dropped below min speed . [ 5 ] fan 2 read - only a 1 indicates that fan 2 has g one above max speed or dropped below min speed . [ 6 ] fan 3 read - only a 1 indicates that fan 3 has g one above max speed or dropped bel ow min speed . [ 7 ] fan 4 read - only a 1 indicates that fan 4 has g one above max speed or dropped below min speed .
adt7470 data sheet rev. e | page 32 of 40 table 34 . register 0x43. fan pulses per revolution register (power - on default = 0x55 ) . bit name read/write description [ 1:0 ] fan 1 read/write sets the number of pulses to be counted when measuring fan 1 spee d. can be used to determine fan s pulses per revolution number for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [ 3:2 ] fan 2 read/write sets the number of pulses to be counted when measuring fan 2 speed. can be used to determine fans pulses per revolution number for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [ 5:4 ] fan 3 read/write s ets the number of pulses to be counted when measuring fan 3 speed. can be used to determine fans pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [ 7:6 ] fan 4 read/write sets the number of pu lses to be counted when measuring fan 4 speed. can be used to determine fans pulses per revolution for unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 table 35. register 0x44 to register 0x57 . temperature limit registers . register address read/write description power - on default 0x44 read/write temperature 1 low limit 0x81 0x45 read/write temperature 1 high limit 0x7f 0x46 read/write temperature 2 low limit 0x81 0x47 read/write temperature 2 high limit 0x7f 0x48 read/write temperature 3 low limit 0x81 0x49 read/write temperature 3 high limit 0x7f 0x4a read/write temperature 4 low limit 0x81 0x4b read/write temperature 4 high limit 0x7f 0x4c read/write temperature 5 low limit 0x81 0x4d read/write temperature 5 high limit 0x7f 0x4e read/write temperature 6 low limit 0x81 0x4f read/write temperature 6 high limit 0x7f 0x50 read/write temperature 7 low limit 0x81 0x51 read/write temperature 7 high limit 0x7f 0x52 read/write temperature 8 low limit 0x81 0x53 read/write temperature 8 high limit 0x7f 0x54 read/write temperature 9 low limit 0x81 0x55 read/write temperature 9 high limit 0x7f 0x56 read/write temperature 10 low limit 0x81 0x57 read/write temperature 10 high limit 0x7f exc eeding any of the temperature limits shown in table 35 by 1c causes the appropriate status bit to be set in the interrupt status registers. high l imits: an interrupt is generated when a value exceeds its high limit ( > comparison ). low l imits: an interrupt is generated when a value is equal to or below its low limit ( co mparison).
data sheet adt7470 rev. e | page 33 of 40 table 36. register 0x58 to register 0x67. fan tachometer limit registers . register address read/write description power - on defa ult 0x58 read/write tach 1 min low byte 0xff 0x59 read/write tach 1 min high byte 0xff 0x5a read/write tach 2 min low byte 0xff 0x5b read/write tach 2 min high byte 0xff 0x5c read/write tach 3 min low byte 0xff 0x5d read/write tach 3 min high byte 0x ff 0x5e read/write tach 4 min low byte 0xff 0x5f read/write tach 4 min high byte 0xff 0x60 read/write tach 1 max low byte 0x00 0x61 read/write tach 1 max high byte 0x00 0x62 read/write tach 2 max low byte 0x00 0x63 read/write tach 2 max high byte 0x0 0 0x64 read/write tach 3 max low byte 0x00 0x65 read/write tach 3 max high byte 0x00 0x66 read/write tach 4 max low byte 0x00 0x67 read/write tach 4 max high byte 0x00 exceeding any of the tach m in limit registers shown in tab le 36 by 1 indicates that the fan is running too slowly or has stalled. th e appropriate status bit is set in interrupt status register 2 to indicate the fan failure. exceeding any of the tach m ax limit registers by 1 indicates that the fan is too fast. t h e appropriate status bit is set in interrupt status register 2 to indicate the fan failure. table 37. register 0x68. pwm 1/ pwm 2 configuration regis ter ( power - on default = 0x00 ) . bit name read/write description [ 0 ] n/a set to 0 (def ault). [ 1 ] n/a set to 0 (default). [ 2 ] n/a set to 0 (default). [ 3 ] n/a set to 0 (default). [ 4 ] inv2 read/write setting this bit to 1 inverts the pwm2 output. default = 0 . [ 5 ] inv1 read/write setting this bit to 1 inverts the pwm1 output. default = 0 . [ 6 ] bhvr2 read/write this bit assigns fan behavior for pwm2 output. 0 = m anual fan control mode (pwm duty cycle controlled in software) . 1 = automatic fan control mode [ 7 ] bhvr1 read/write this bit assigns fan behavior for pwm1 output. 0 = m anual fan con trol mode (pwm duty cycle controlled in software) . 1 = automatic fan control mode.
adt7470 data sheet rev. e | page 34 of 40 table 38 . register 0x69. p wm3/ pwm 4 configuration register ( power - on default = 0x00 ) . bit name read/write description [ 0 ] n/a set to 0 (default). [ 1 ] n/a set to 0 (default). [ 2 ] n/a set to 0 (default). [ 3 ] n/a set to 0 (default). [ 4 ] inv4 read/write setting this b it to 1 inverts the pwm4 output. default = 0 [ 5 ] inv3 read/write setting this b it to 1 inverts the pwm3 output. default = 0 [ 6 ] bhv r4 read/write this bit assigns fan behavior for pwm4 output. 0 = m anual fan control mode (pwm duty cycle controlled in software) . 1 = (automatic fan control mode. [ 7 ] bhvr3 read/write this bit assigns fan behavior for pwm3 output. 0 = m anual fan control m ode (pwm duty cycle controlled in software) . 1 = automatic fan control mode. table 39 . register 0x6a to register 0x6d. pwm min duty cycle registers ( power - on default = 0x80 (50% duty cycle ) . register address read/write description 0x6a read/write pwm1 min duty cycle . 0x6b read/write pwm2 min duty cycle . 0x6c read/write pwm3 min duty cycle . 0x6d read/write pwm4 min duty cycle . table 40. p wm min duty cycle register s detailed description bit name read/write d escription [ 7:0 ] pwm duty cycle read/write these bits define the pwnmin duty cycle for pwmx (x = 1 to 4) . 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xff = 100% pmw max duty cycle (full fan speed). table 41. register 0x6e to register 0x71. t min registers ( power - on default = 0x5a (90c ) ) . register address read/write description 0x6e read/write temperature 1 t min . 0x6f read/write temperature 2 t min . 0x70 read/write temperature 3 t min . 0x71 read/write temperature 4 t min . table 41 shows the t min registers for each thermal zone. when the temperature measured exceeds t min , the appropriate fan runs at minimum speed (pwm min ). they increase to maximum speed (pwm ma x ) at t min + 20c.
data sheet adt7470 rev. e | page 35 of 40 table 42. register 0x72. i nterrupt mask register 1 (power - on default = 0x00 ) . bit name read/write description [ 7 ] not in use read/write not in use. write 0 to this bit. [ 6 ] r 7 t read/write a 1 masks the temperat ure 7 value from generating an interrupt on the smbalert output. the r1t bit is set as normal in the status register for out - of - limit conditions. [ 5 ] r 6 t read/write a 1 masks the temperature 6 value from generating an interrupt on t he smbalert output. the r2t bit is set as normal in the status register for out - of - limit conditions. [ 4 ] r 5 t read/write a 1 masks the temperature 5 value from generating an interrupt on the smbalert output. th e r3t bit is set as normal in the status register for out - of - limit conditions. [ 3 ] r4t read/write a 1 masks the temperature 4 value from generating an interrupt on the smbalert output. the r4t bit is set as normal in the status regi ster for out - of - limit conditions. [ 2 ] r 3 t read/write a 1 masks the temperature 3 value from generating an interrupt on the smbalert output. the r5t bit is set as normal in the status register for out - of - limit conditions. [ 1 ] r 2 t re ad/write a 1 masks the temperature 2 value from generating an interrupt on the smbalert output. the r6t bit is set as normal in the status register for out - of - limit conditions. [ 0 ] r 1 t read/write a 1 masks the temperature 1 value fr om generating an interrupt on the smbalert output. the r7t bit is set as normal in the status register for out - of - limit conditions. table 43 . register 0x73. i nterrupt mask register 2 (power - on default = 0x 00) . bit name read/write description [ 7 ] fan 4 read/write a 1 masks the fan 4 value from generating an interrupt on the smbalert output. the fan 4 bit is set as normal in the status register for out - of - limit conditions. [ 6 ] fan 3 rea d/write a 1 masks the fan 3 value from generating an interrupt on the smbalert output. the fan 3 bit is set as normal in the status register for out - of - limit conditions. [ 5 ] fan 2 read/write a 1 masks the fan 2 value from generatin g an interrupt on the smbalert output. the fan 2 bit is set as normal in the status register for out - of - limit conditions. [ 4 ] fan 1 read/write a 1 masks the fan 1 value from generating an interrupt on the smbale rt output. the fan 1 bit is set as normal in the status register for out - of - limit conditions. [ 3 ] daisy chain read/write a 1 masks the pulsing of the smbalert while enabling daisy chain, writing to bit [7] register 0x40 . [ 2 ] r10 t read/write a 1 masks the temperature 10 value from generating an interrupt on the smbalert output. the r10t bit is set as normal in the status register for out - of - limit conditions. [ 1 ] r9t read/write a 1 masks the temperature 9 va lue from generating an interrupt on the smbalert output. the r9t bit is set as normal in the status register for out - of - limit conditions. [ 0 ] r8t read/write a 1 masks the temperature 8 value from generating an interrupt on the smbalert output. the r8t bit is set as normal in the status register for out - of - limit conditions.
adt7470 data sheet rev. e | page 36 of 40 table 44. register 0x74. configuration register 2 (power - on default = 0x00 ) . bit name read/write description [ 7 ] shdn read/write shutdown/low current mode . [ 6:4 ] freq read/write these bits control pwm1 C pwm 4 frequency when the fan drive is configured as a low frequency drive. register 0x74 [ 6:4 ] register 0x40 [ 6 ] = 1 register 0x40 [ 6 ] = 0 000 11.0 hz 1.4 khz 001 14.7 hz 22.5 khz 010 22.1 hz 22.5 khz 011 29.4 hz 22.5 khz 100 35.3 hz 22.5 khz 101 44.1 hz 22.5 khz 110 58.8 hz 22.5 khz 111 88.2 hz 22.5 khz [ 3 ] t4_dis read/write writing a 1 disables tach 4 measurements . [ 2 ] t3_dis read/write writ ing a 1 disables tach 3 measurements . [ 1 ] t2_dis read/write writing a 1 disables tach 2 measurements . [ 0 ] t1_dis read/write writing a 1 disables tach 1 measurements . table 45. register 0x78. max tmp05 temperature (power - on defaul t = 0x00 ) . bit name read/write description [ 7:0 ] tmp05_max read - only this register indicates the maximum of all tmp05 temperatures. table 46. register 0x7c. tmp05 zone select 1 (power - on default = 0x00 ) . bit name read/write descri ption [ 7:4 ] zone_fan1 [ 3:0 ] read/write these bits determine w hich temperature zone controls fan 1. zone_fan1 [ 3:0 ] description 0000 m ax_temperature from register 0x78 controls fan 1. 0001 temperature 1 from register 0x20 controls fan 1 . 0010 tem perature 2 from register 0x21 controls fan 1 . 0011 temperature 3 from register 0x22 controls fan 1 . 0100 temperature 4 from register 0x23 controls fan 1 . 0101 temperature 5 from register 0x24 controls fan 1 . 0110 temperature 6 from register 0x2 5 controls fan 1 . 0111 temperature 7 from register 0x26 controls fan 1 . 1000 temperature 8 from register 0x27 controls fan 1 . 1001 temperature 9 from register 0x28 controls fan 1 . 1010 temperature 10 from register 0x29 controls fan 1 . [ 3:0 ] zo ne_fan2 [ 3:0 ] read/write these bits determine w hich temperature zone controls f an 2 . zone_fan2 [ 3:0 ] description 0000 max_ temperature from register 0x78 controls fan 2. 0001 temperature 1 from register 0x20 controls fan 2. 0010 temperature 2 fro m register 0x21 controls fan 2. 0011 temperature 3 from register 0x22 controls fan 2. 0100 temperature 4 from register 0x23 controls fan 2. 0101 temperature 5 from register 0x24 controls fan 2. 0110 temperature 6 from register 0x25 controls fan 2. 0111 temperature 7 from register 0x26 controls fan 2. 1000 temperature 8 from register 0x27 controls fan 2. 1001 temperature 9 from register 0x28 controls fan 2. 1010 temperature 10 from register 0x29 controls fan 2.
data sheet adt7470 rev. e | page 37 of 40 table 47. register 0x7d. tmp05 zone select 2 (power - on default = 0x00 ) . bit name read/write description [ 7:4 ] zone_fan3 [ 3:0 ] read/write these bits determine which temperature zone controls fan 3. zone_fan3 [ 3:0 ] description 0000 m ax_temperature from register 0x78 controls fan 3. 0001 temperature 1 from register 0x20 controls fan 3. 0010 temperature 2 from register 0x21 controls fan 3. 0011 temperature 3 from register 0x22 controls fan 3. 0100 temperature 4 from register 0x23 controls fan 3. 0101 temperature 5 from register 0x 24 controls fan 3. 0110 temperature 6 from register 0x 25 controls fan 3. 0111 temperature 7 from register 0x 26 controls fan 3. 1000 temperature 8 from register 0x 27 controls fan 3. 1001 temperature 9 from register 0x 28 controls fan 3. 1010 temperature 10 from register 0x 29 controls fan 3. [ 3:0 ] zone_fan4 [ 3:0 ] read/write these bits determine which temperature zone controls fan 4. zone_fan4 [ 3:0 ] description 0000 m ax_temperature from registe r 0x 78 controls fan 4. 0001 temperature 1 from register 0x 20 controls fan 4. 0010 temperature 2 from register 0x 21 controls fan 4. 0011 temperature 3 from register 0x 22 controls fan 4. 0100 temperature 4 from register 0x 23 controls fan 4. 0101 temperature 5 from register 0x 24 controls fan 4. 0110 temperature 6 from register 0x 25 controls fan 4. 0111 temperature 7 from register 0x 26 controls fan 4. 1000 temperature 8 from register 0x 27 controls fan 4. 1001 temperature 9 from regist er 0x 28 controls fan 4. 1010 temperature 10 from register 0x 29 controls fan 4. table 48 . register 0x7f. gpio enable (power - on default = 0x00 ) . bit name read/write description [ 7:6 ] reserved read/write reserved. write 0x0 to th ese bits. [ 5:4 ] reserved read/write reserved. this bit should be set to 0. [ 3 ] gpio 1_en read/write pwm 1 becomes a gpio. [ 2 ] gpio 2_en read/write pwm 2 becomes a gpio. [ 1 ] gpio 3_en read/write pwm 3 becomes a gpio. [ 0 ] gpio 4_en read/write pwm 4 becomes a gp io.
adt7470 data sheet rev. e | page 38 of 40 t able 49 . register 0x80. gpio config (power - on default = 0x00 ) . bit name read/write description [ 7 ] gpio 1_d read/write this bit s ets the direction of gpio 1 when the pwm 1 pin is configured as gpio. 1 = output; 0 = input. data for gpio 1 is set by the lsb of the pwm 1 min duty cycle register. [ 6 ] gpio 1_p read/write this b it sets the polarity of gpio 1 when the pwm1 pin is configured as gpio. 1 = active high; 0 = active low. [ 5 ] gpio 2_d read/write this bi t sets the direction o f gpio 2 when the pwm2 pin is configured as gpio. 1= output; 0 = input. data for gpio 2 is set by the lsb of the pwm 2 min duty cycle register. [ 4 ] gpio 2_p read/write this b it sets the polarity of gpio 2 when the pwm2 pin is configured as gpio. 1 = active high; 0 = active low. [ 3 ] gpio 3_d read/write this bi t sets the direction of gpio 3 when the pwm3 pin is configured as gpio. 1= output; 0 = input. data for gpio 3 is set by the lsb of the pwm 3 min duty cycle register. [ 2 ] gpio 3_p read/write th is b it sets the polarity of gpio 3 when the pwm3 pin is configured as gpio. 1 = active high; 0 = active low. [ 1 ] gpio 4_d read/write this bi t sets the direction of gpio 4 when the p wm4 pin is configured as gpio. 1= output; 0 = input. data for gpio 4 is s et by the lsb of the pwm4 min duty cycle register. [ 0 ] gpio 4_p read/write this b it sets the polarity of gpio 4 when the pwm 4 pin is configured as gpio. 1 = active high; 0 = active low. table 50 . register 0x81. gpio status (power - on default = 0x00 ) . bit name read/write description [ 7 :4 ] gpio_s read/write th ese bit s indicate the status of the gpio when the corresponding pwm pin is configured as gpio. when gpio is configured as an input, these bits are read - only. they are set when the input is asserted. (asserted can be high or low depending on the setting of the gpio polarity.) when gpio is configured as an output, these bits are read/write. setting these bits asserts the gpio output. (asserted can be high or low depending on the s etting of gpio4 polarity.) [ 7 ] gpio 4_s read/write this bit indicates the status of gpio 4 when the pwm4 pin is configured as gpio. [ 6 ] gpio 3_s read/write this bit indicates the status of gpio 3 when the pwm3 pin is configured as gpio. [ 5 ] gpio 2_s read/w rite this bit indicates the status of gpio 2 when the pwm2 pin is configured as gpio. [ 4 ] gpio 1_s read/write this bit indicates the status of gpio 1 when the pwm1 pin is configured as gpio. [ 3:0 ] r eserved read/write test bit. for a nalog devices use only.
data sheet adt7470 rev. e | page 39 of 40 outline dimensions compliant to jedec standards mo-137-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 16 9 8 1 seating plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarity 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.197 (5.00) 0.193 (4.90) 0.189 (4.80) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 01-28-2008-a figure 25. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option adt7470arqz ?40c to +125c 16-lead qsop rq-16 adt7470arqz-reel ?40c to +125c 16-lead qsop rq-16 adt7470arqz-reel7 ?40c to +125c 16-lead qsop rq-16 EVAL-ADT7470EBZ evaluation board 1 z = rohs compliant part.
adt7470 data sheet rev. e | page 40 of 40 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2004 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04684 - 0- 4/13(e)

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